The invention relates to a parity bit extraction/insertion system that processes the data in parallel using a single clock signal.
A data receiver typically uses a parity extraction circuit to locate a parity bit contained in a parallel bit stream of data bytes. Usually, the parity bit is the Nth bit in the parallel bit stream, for example, the 65th bit. The parity bit, as is well-known, gives the parity, odd or even, for the preceding bits of the parallel bit stream.
The location of the parity bit may be readily determined by converting the parallel bit stream to a serial bit stream to count the data bits in a conventional manner. The data bit occupying the 65th bit position in the serial stream would then be extracted as the parity bit. It is noted that if the data bytes are received and converted into a serial bit stream at a first clock rate, e.g., a rate of x bits/second, then, they must be counted at a higher data rate of at least mx bits/second. What this means is that at the circuit level, a clock boundary would exist between the two clock rates at the input and at the output of the parity bit extractor circuit.
As is well-known, a designer may use a number of different commercially available software tools to design an Application Specific Integrated Circuit (ASIC). These tools include, for example, timing analysis software, gate synthesis software, layout software, etc. Disadvantageously, such software is not particularly adapted to handle a circuit containing a clock boundary. To deal with this shortcoming, a designer has to partition the circuit at the clock boundary and synthesize the partitioned sections independently using the software tools. However, the timing analysis between the sections as well as the gate synthesis and layout of the interface between the sections must be done manually, which is, indeed, an arduous and complex task to complete properly.
It is apparent from the foregoing that the clock boundary problem would also be applicable to a parity bit insertion circuit.
The design of data network apparatus on an ASIC is greatly enhanced, in accordance with the invention, by using a parity bit extraction circuit and a parity bit insertion circuit which employ a single clock signal and do not convert the incoming parallel data stream into a serial data stream.
These and other aspects of the claimed invention will be appreciated from the ensuing detailed description and accompanying drawings.